India's semiconductor ambitions run into a transparency wall — and Congress MP Dr. Shashi Tharoor is pressing Parliament to see through it. On Tuesday, August 11, 2026, Tharoor called out the Ministry of Electronics and Information Technology for delivering a response to his unstarred question that, in his words, was 'inadequate at best' — long on headline figures, short on the outcomes that actually matter.

What the Ministry said — and what it left out

The Ministry's reply cited 105 companies granted access to design software, 24 product design projects approved, and 25 chip designs sent for tape-out. On the surface, those numbers look like momentum. But Tharoor's question cut deeper: of those 25 designs that reached tape-out, how many actually became working, deployable products? The Ministry offered no answer. 'The answer provides no such breakdown and instead offers only a broad overview,' Tharoor wrote, pointing to the gap between reaching a design stage and delivering a commercially viable chip. Equally absent from the reply, he noted, was any granular data on the Product Design Linked Incentive and Deployment Linked Incentive components — specifically, how many applicants became eligible for incentives versus how many actually received disbursements. That applicant-to-disbursement ratio is precisely the metric that separates a functioning scheme from one that exists largely on paper.

Semicon 2.0's Rs 1.27 lakh crore figure cannot paper over unanswered questions

Rather than addressing implementation gaps, the Ministry's reply pivoted to announcing the outlay for what Tharoor refers to as Semicon 2.0 — a Rs 1.27 lakh crore headline figure for the next phase of India's semiconductor push. Tharoor was pointed in his pushback: 'A bigger scheme cannot substitute for transparency on the outcomes of the current one.' The critique lands in a specific policy context. India's original Semicon India programme, approved by the Union Cabinet in December 2021 with an outlay of Rs 76,000 crore, was designed to build domestic capabilities across fabrication, packaging, and chip design. The Design Linked Incentive (DLI) Scheme, notified under that umbrella, offered fiscal support to Indian fabless companies and design startups. Five years on, the question of how many of those startups moved from incentive eligibility to actual disbursement — and from disbursement to a product on a shelf — remains, by Tharoor's account, unanswered in Parliament.

Why disbursement-level data is the real scoreboard

India's semiconductor strategy sits at the intersection of industrial policy and geopolitical urgency — a direct response to the supply-chain shocks that exposed the world's dependence on a handful of chip-making nodes. Parliamentary oversight is one of the few mechanisms that can force disbursement-level accountability into public view. When a ministry responds to a specific question on outcomes with a list of approvals and a new scheme announcement, it substitutes ambition for evidence. Tharoor's closing line in his post was unambiguous: 'India's semiconductor design ecosystem needs clear, disbursement-level accountability, not just fresh announcements layered atop unanswered questions.' The semiconductor design startups and fabless companies that applied under the DLI scheme — and whose futures depend on whether those incentives actually flow — are owed that answer. The Ministry of Electronics and Information Technology has yet to provide a supplementary response. Whether it does — and how specific that response is — will say more about the DLI scheme's real-world progress than any headline figure.