Peking University EDA tool targets Huawei's 1.4nm chip goal by 2031
Synopsis
Peking University has unveiled a prototype EDA chip-design tool built to work with Huawei's new LogicFolding architecture — the most direct academic challenge yet to Western EDA giants Synopsys and Cadence, as Huawei races to hit 1.4nm performance by 2031 without US tools.
Key Takeaways
Peking University's School of Integrated Circuits announced a prototype EDA tool on 27 May 2026 compatible with Huawei 's LogicFolding architecture.
Huawei aims to produce chips matching 1.4-nanometre performance by 2031 without Western chipmaking tools restricted under US export controls.
Huawei 's Tau (τ) Scaling Law prioritises signal speed and reduced resistance over transistor shrinkage, a direct response to being cut off from advanced lithography machines.
The global EDA market is dominated by US firms Synopsys and Cadence Design Systems , both subject to export restrictions limiting their use in advanced Chinese chip development.
The prototype represents Beijing 's most prominent university-led push to build a self-contained semiconductor design ecosystem independent of Western software.
Peking University's School of Integrated Circuits unveiled a prototype electronic design automation (EDA) tool on Tuesday, 27 May 2026, claiming a breakthrough in domestic chip design software that is directly compatible with Huawei Technologies' new semiconductor architecture — a development that could meaningfully advance China's push to build cutting-edge chips without Western tools.
What was announced
The new EDA tool is designed to work with Huawei's LogicFolding architecture, which the company introduced on Monday, 26 May 2026. EDA software is the highly specialised engineering platform used to design and test microchips before they enter manufacturing, and the global market for it is dominated by US-based firms Synopsys and Cadence Design Systems. Developing a credible domestic alternative has become a strategic priority for Beijing as Western export controls tighten.
Huawei's Tau Scaling Law strategy
Huawei's stated goal is to produce chips by 2031 that match the performance of advanced 1.4-nanometre technology — entirely without relying on restricted Western chipmaking tools. To achieve this, the company has pivoted away from the decades-old industry approach of shrinking transistors to improve performance. After Washington blocked China from acquiring advanced lithography machines, Huawei adopted a new framework called the Tau (τ) Scaling Law, which focuses on accelerating the speed of electrical signals across a chip by reducing resistance and tightening internal wiring rather than reducing physical transistor size.
Why it matters
The convergence of a domestically developed EDA tool with Huawei's proprietary architecture signals a deliberate attempt to build a self-contained semiconductor design ecosystem inside China. US-led export restrictions have cut off access to both advanced fabrication equipment and leading design software, making indigenous EDA capability a critical missing link. The Peking University announcement, according to the university's official release, positions the prototype as a direct response to that gap.
The competitive backdrop
Synopsys and Cadence Design Systems together command the overwhelming majority of the global EDA market, and both are subject to US export controls that restrict their software's use in advanced Chinese chip development. China has made repeated attempts to cultivate domestic EDA players, but none has yet achieved parity with Western incumbents at the leading edge. The Peking University prototype, described as compatible with Huawei's 3D LogicFolding design approach, represents the most publicly prominent university-led effort to date.
What's next
The prototype's path from academic announcement to industrial deployment remains the key question — EDA tools require years of validation before chipmakers rely on them for production-grade designs. Whether Huawei's Huawei Scientist Committee formally integrates the Peking University tool into its development pipeline, and at what timeline, will determine how much practical weight Tuesday's announcement carries. Observers will also watch whether Synopsys and Cadence face further restrictions that could accelerate demand for domestic alternatives.
Point of View
And no Chinese EDA vendor has yet closed that gap at the leading edge. The more significant signal is architectural: by designing the Tau Scaling Law and LogicFolding around constraints imposed by US export controls, Huawei is effectively letting the chip war dictate its engineering roadmap — a strategic adaptation that could, if successful, erode the leverage Washington derives from controlling lithography and EDA chokepoints. The 2031 target date is long enough to be credible but short enough to maintain urgency inside China's semiconductor industrial policy cycle.
NationPress
12 Jul 2026
Frequently Asked Questions
What did Peking University announce about chip design software?
Peking University's School of Integrated Circuits unveiled a prototype electronic design automation (EDA) tool on 27 May 2026. The tool is compatible with Huawei's new LogicFolding architecture and is intended to support China's efforts to design advanced semiconductors without relying on Western EDA software from companies like Synopsys and Cadence Design Systems.
What is Huawei's LogicFolding architecture?
LogicFolding is a new chip architecture introduced by Huawei on 26 May 2026. It forms part of Huawei's broader Tau (τ) Scaling Law strategy, which focuses on improving chip performance by accelerating electrical signal speed and reducing internal wiring resistance, rather than shrinking transistors — the traditional industry method now blocked for Huawei by US export controls on advanced lithography equipment.
Why is China developing its own EDA software?
China is developing domestic EDA software because the global market is dominated by US firms Synopsys and Cadence Design Systems, both subject to American export restrictions that limit their use in advanced Chinese semiconductor development. Without EDA tools, Chinese chipmakers cannot design leading-edge chips regardless of fabrication capability, making indigenous EDA a critical strategic priority for Beijing.
What is Huawei's 1.4nm chip target and when does it plan to achieve it?
Huawei's stated goal is to produce chips that match the performance of advanced 1.4-nanometre technology by 2031. The company intends to achieve this entirely without Western chipmaking tools that are currently restricted under US export controls, relying instead on its Tau Scaling Law approach and compatible domestic design software.
How does the Peking University EDA tool affect competition with Synopsys and Cadence?
The Peking University prototype is the most publicly prominent university-led challenge to date against Western EDA incumbents Synopsys and Cadence. However, a significant gap remains between an academic prototype and a production-grade tool capable of handling leading-edge chip designs; industrial validation typically takes years, meaning the competitive impact on Synopsys and Cadence will depend heavily on how quickly the tool can be hardened for real manufacturing pipelines.
