Union Education Minister Dharmendra Pradhan announced on Wednesday, 15 July 2026 that the Union Cabinet has approved Semicon 2.0, a sweeping semiconductor policy package carrying an outlay of ₹1.27 lakh crore, building on the earlier Semicon 1.0 initiative to position India as a global hub for chip design and manufacturing.

Context

Pradhan, posting on X, described the Cabinet decision as a reaffirmation of Prime Minister Narendra Modi's commitment to make India a 'global semiconductor powerhouse.' The announcement comes as India seeks to reduce dependence on imported chips and capitalise on shifting global supply chains accelerated by US-China technology tensions and post-pandemic disruptions.

Semicon 2.0 is structured around six pillars: chip design ecosystem development, machines and materials supply chain, next-generation fabrication (Fabs), advanced chip packaging through ATMP/OSAT facilities, research and development in advanced nodes, and talent development. On the talent front, the minister highlighted that 315 universities and nearly 68,000 students have already been trained under the programme's preceding phase.

Policy Backdrop

India's semiconductor push dates to 2021, when the India Semiconductor Mission (ISM) was launched with an initial outlay of ₹76,000 crore to build a domestic ecosystem spanning manufacturing, design, and packaging. The Make in India programme, launched in 2014, laid the broader industrial policy foundation that semiconductor policy now builds upon.

Production Linked Incentive schemes for IT hardware and the expansion of Electronics Manufacturing Clusters have progressively strengthened the supply-chain infrastructure that Semicon 2.0 now seeks to scale. The new package significantly raises the fiscal commitment, signalling a step-change in ambition from the earlier mission.

Pradhan's role as Education Minister is directly relevant to the talent pillar — universities under the Ministry of Education are central to the trained-workforce pipeline that semiconductor firms require before committing capital to India-based facilities.

Stakeholders and Impact

Global semiconductor firms scouting for geopolitically stable manufacturing and design bases stand to be the primary beneficiaries of the expanded incentive framework. Indian engineering universities and technical institutions are positioned as key delivery partners for the talent component, with the 315-university network already activated under prior phases.

Advanced chip packaging — the ATMP/OSAT segment — is seen as India's nearest-term entry point into the global semiconductor value chain, given lower capital requirements compared to front-end fabrication. Semicon 2.0's explicit pillar for this segment suggests the government intends to accelerate approvals and incentives in this area specifically.

Domestic electronics manufacturers and startups in the chip design space are also likely to benefit from the design ecosystem pillar, which targets scaling India's existing but nascent fabless design industry.

What's Next

Detailed scheme guidelines from the Cabinet notification are expected to specify eligibility criteria, incentive structures, and timelines for each of the six pillars. State governments with existing semiconductor ambitions — including those that have already fielded fab proposals — are likely to move quickly to align their own incentive packages with the central framework.

Memoranda of understanding with global chip companies for design centres and ATMP facilities will be a key metric of early traction. With ₹1.27 lakh crore committed, Semicon 2.0 sets a high bar — and the pace of private investment announcements in the months ahead will determine whether India's semiconductor ambitions translate from policy into production lines.