Vaishnaw Unveils Semicon 2.0 With ₹1.27 Lakh Cr Outlay
Synopsis
Key Takeaways
Union Minister Ashwini Vaishnaw on Thursday, 16 July 2026 announced Semicon 2.0, a revamped semiconductor policy package with a total outlay of ₹1,27,500 crore, structured around six strategic pillars aimed at building a self-reliant chip ecosystem in India.
Context
In his post on X, Vaishnaw outlined the six pillars of Semicon 2.0: chip design, machines and materials, more fabrication units (fabs), strengthening ATMP/OSAT (assembly, testing, marking, and packaging / outsourced semiconductor assembly and test), research and development, and talent development. The announcement signals a significant scaling-up of India's ambitions in the global semiconductor value chain.
The six-pillar structure reflects a deliberate effort to address the full spectrum of semiconductor manufacturing — from the earliest design stage to the final packaging and testing of chips, as well as the human capital needed to sustain the industry long-term.
Policy Backdrop
Semicon 2.0 builds on the original India Semiconductor Mission (ISM), approved in December 2021 under the Ministry of Electronics and Information Technology (MeitY) with an initial outlay of approximately ₹76,000 crore. That programme sought to attract wafer fabrication plants and design-linked investments through fiscal incentives, making India a viable alternative to established East Asian chip-manufacturing hubs.
The new package, at ₹1,27,500 crore, represents a substantial increase over the original commitment, reflecting lessons learned from the first phase and the heightened global race to secure domestic semiconductor supply chains. India's approach draws broad parallels with the US CHIPS and Science Act and the EU Chips Act, while remaining anchored in the government's Atmanirbhar Bharat framework. The Production Linked Incentive (PLI) scheme for electronics, launched in 2020, laid earlier groundwork by incentivising mobile phone and component manufacturing.
Stakeholders and Impact
The policy is expected to have direct implications for domestic and global semiconductor firms, electronics manufacturers, and engineering graduates seeking careers in chip design and fabrication. The explicit inclusion of talent development as a dedicated pillar signals that the government recognises workforce capacity as a binding constraint alongside capital and technology.
The ATMP/OSAT pillar is particularly significant: assembly, testing, and packaging operations are often the entry point for countries building semiconductor capabilities, and strengthening this segment can attract global chip companies looking to diversify their supply chains away from concentrated East Asian production bases. A dedicated pillar for machines and materials also suggests intent to reduce dependence on imported semiconductor equipment and specialty chemicals.
What's Next
Attention will now turn to the disbursement timelines, eligibility criteria, and incentive structures that will govern the ₹1,27,500 crore outlay across the six pillars. Announcements of specific fab projects, design centre investments, and international technology partnerships are likely to follow as the policy framework is operationalised through MeitY.
If executed at scale, Semicon 2.0 could position India as a meaningful node in the global semiconductor supply chain by the end of this decade — a strategic outcome that carries both economic and national-security implications for the country's technology sovereignty.